The invention relates to a semiconductor memory, in particular a DRAM (Dynamic Random Access Memory), and to a measuring method for a semiconductor memory.
In DRAMS, the respective memory cells may e.g. consist substantially of capacitors. The memory cells/capacitors are adapted to be connected to bit lines which serve to transmit a data value to be read out from a memory cell, or a data value to be read into the memory cell.
During the reading out of a memory cell, an access transistor that is connected with the capacitor of a memory cell is connected through by the activation of a word line, and the charge state stored in the capacitor is applied to the bit line.
Subsequently, the weak signal emanating from the capacitor is amplified by a sense amplifier. The sense amplifier comprises complementary signal inputs. The bit lines connected to these signal inputs are referred to as bit line and complementary bit line.
In today's DRAMS, the sense amplifiers may be used as “shared parts” so as to save chip space. In so doing, a sense amplifier is used both during the reading out of a memory cell positioned at the left and a memory cell positioned at the right side along respective bit lines associated with the sense amplifier (hence, the sense amplifiers are used as so-called “shared sense amplifiers”).
Prior to the reading out of the memory cells, the corresponding bit line sections, i.e. the corresponding sections of the non-complementary bit line and of the complementary bit line, are, by so-called precharge/equalize circuits that are connected with the bit lines, precharged to the same potential. The precharge potential may correspond to half the voltage of a bit line in a logic high state (i.e. to VBLH/2). This ensures that—prior to the reading out of data—no differences occur between the potential of the section of the bit line and the section of the corresponding complementary bit line, which otherwise might superimpose the small amount of charge transferred by the capacitor of a memory cell to the bit lines during reading out. Directly prior to the reading out of the memory cells the pre-charge/equalize circuits which are connected to the bit line sections that are connected with the memory cell to be read out are switched off.
The DRAMs known in prior art moreover include isolation circuits with isolation transistors, which serve to decouple the sense amplifier during the reading out of the memory cells from the side/the bit line sections that is/are not connected to memory cells to be read out.
Each isolation circuit may, for instance, consist of two NMOS-FETs, the source-drain paths of which are adapted to interrupt the corresponding bit line sections.
With the known DRAMs, outside the read and write cycles, corresponding bias voltages are applied to the gates of the isolation transistors of the isolation circuits. These bias voltages may e.g. correspond to a voltage (VINT) generated internally in the DRAM.
Directly prior to the reading out of a memory cell, the side of the sense amplifier which is connected with the memory cells not to be read out is coupled off the respective bit line section(s) by the gates of the corresponding isolation transistors positioned on this side of the sense amplifier being put to ground. Simultaneously, the other side of the sense amplifier may be coupled electrically to the corresponding bit line section(s) by the gate voltage that is applied to the gates of the isolation transistors positioned on the other side of the sense amplifier being increased e.g. from its above initial value VINT to a voltage value VPP.
The actual reading out of the memory cell is initiated shortly thereafter by appropriate word line signals connecting through the access transistors that are connected with the storage capacitors. Subsequently, appropriate activating voltages are applied to the sense amplifier, whereupon the sense amplifier amplifies the potential differences transmitted from the storage capacitors to the corresponding bit line sections, and outputs a corresponding amplified differential signal.
The correspondingly amplified differential signal is transmitted from the sense amplifier to corresponding local data lines which are adapted to be coupled to the sense amplifier by appropriate transistors.
The above-mentioned amplified differential signal is transmitted from the local data lines to corresponding global data lines, and to a further amplifier (so-called “secondary sense amplifier”) for further amplification.
To enable a quick reading out of data from the memory cells, or a quick reading of data into the memory cells, respectively, the capacitors of the memory cells must be capable of being discharged or charged quickly (e.g. in the range of nano seconds).
If the (current) path connected with the capacitor of a memory cell comprises a relatively high (series) resistance value, quick charging/discharging of the capacitor is prevented by the resulting relatively large RC constant.
The above-mentioned series resistance value is substantially caused by the ohmic resistance of the connection between the memory cell capacitor and the respective memory cell access transistor.
For the above mentioned reasons, it is desirable to be able to measure the above-mentioned series resistance value or the above-mentioned RC constant, respectively, as exactly as possible, in particular with corresponding or similar frequencies as in normal operation of the semiconductor memory.